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@ -24,6 +24,8 @@ |
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#define CMT2300A_MASK_LOCKING_EN 0x20 |
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#define CMT2300A_MASK_LOCKING_EN 0x20 |
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#define CMT2300A_MASK_CHIP_MODE_STA 0x0F |
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#define CMT2300A_MASK_CHIP_MODE_STA 0x0F |
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#define CMT2300A_CUS_CMT10 0x09 |
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#define CMT2300A_CUS_MODE_CTL 0x60 // [7] go_switch
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#define CMT2300A_CUS_MODE_CTL 0x60 // [7] go_switch
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// [6] go_tx
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// [6] go_tx
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// [5] go_tfs
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// [5] go_tfs
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@ -152,6 +154,28 @@ |
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#define CMT2300A_MASK_PKT_OK_FLG 0x01 |
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#define CMT2300A_MASK_PKT_OK_FLG 0x01 |
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// default CMT paramters
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// default CMT paramters
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/*static uint8_t cmtConfig[0x60] PROGMEM {
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// 0x00 - 0x0f -- RSSI offset +- 0 and 13dBm
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0x00, 0x66, 0xEC, 0x1C, 0x70, 0x80, 0x14, 0x08, |
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0x11, 0x02, 0x02, 0x00, 0xAE, 0xE0, 0x35, 0x00, |
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// 0x10 - 0x1f
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0x00, 0xF4, 0x10, 0xE2, 0x42, 0x20, 0x0C, 0x81, |
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0x42, 0x32, 0xCF, 0x82, 0x42, 0x27, 0x76, 0x12, // 860MHz as default
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// 0x20 - 0x2f
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0xA6, 0xC9, 0x20, 0x20, 0xD2, 0x35, 0x0C, 0x0A, |
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0x9F, 0x4B, 0x29, 0x29, 0xC0, 0x14, 0x05, 0x53, |
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// 0x30 - 0x3f
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0x10, 0x00, 0xB4, 0x00, 0x00, 0x01, 0x00, 0x00, |
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0x12, 0x1E, 0x00, 0xAA, 0x06, 0x00, 0x00, 0x00, |
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// 0x40 - 0x4f
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0x00, 0x48, 0x5A, 0x48, 0x4D, 0x01, 0x1D, 0x00, |
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0x00, 0x00, 0x00, 0x00, 0xC3, 0x00, 0x00, 0x60, |
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// 0x50 - 0x5f
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0xFF, 0x00, 0x00, 0x1F, 0x10, 0x70, 0x4D, 0x06, |
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0x00, 0x07, 0x50, 0x00, 0x42, 0x0C, 0x3F, 0x7F // - TX 13dBm
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};*/ |
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// LP Settings
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static uint8_t cmtConfig[0x60] PROGMEM { |
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static uint8_t cmtConfig[0x60] PROGMEM { |
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// 0x00 - 0x0f -- RSSI offset +- 0 and 13dBm
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// 0x00 - 0x0f -- RSSI offset +- 0 and 13dBm
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0x00, 0x66, 0xEC, 0x1C, 0x70, 0x80, 0x14, 0x08, |
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0x00, 0x66, 0xEC, 0x1C, 0x70, 0x80, 0x14, 0x08, |
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@ -173,6 +197,7 @@ static uint8_t cmtConfig[0x60] PROGMEM { |
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0x00, 0x07, 0x50, 0x00, 0x42, 0x0C, 0x3F, 0x7F |
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0x00, 0x07, 0x50, 0x00, 0x42, 0x0C, 0x3F, 0x7F |
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}; |
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}; |
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enum {CMT_SUCCESS = 0, CMT_ERR_SWITCH_STATE, CMT_ERR_TX_PENDING, CMT_FIFO_EMPTY, CMT_ERR_RX_IN_FIFO}; |
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enum {CMT_SUCCESS = 0, CMT_ERR_SWITCH_STATE, CMT_ERR_TX_PENDING, CMT_FIFO_EMPTY, CMT_ERR_RX_IN_FIFO}; |
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template<class SPI> |
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template<class SPI> |
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@ -292,8 +317,12 @@ class Cmt2300a { |
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mSpi.writeFifo(buf, len); |
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mSpi.writeFifo(buf, len); |
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// send only on base frequency: here 863.0 MHz
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if(0xff != mRqstCh) { |
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//switchChannel((len != 15));
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DPRINTLN(DBG_INFO, "switchChannel: 0x" + String(mRqstCh, HEX)); |
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mCurCh = mRqstCh; |
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mRqstCh = 0xff; |
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} |
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mSpi.writeReg(CMT2300A_CUS_FREQ_CHNL, mCurCh); |
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if(!cmtSwitchStatus(CMT2300A_GO_TX, CMT2300A_STA_TX)) |
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if(!cmtSwitchStatus(CMT2300A_GO_TX, CMT2300A_STA_TX)) |
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return CMT_ERR_SWITCH_STATE; |
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return CMT_ERR_SWITCH_STATE; |
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@ -319,6 +348,9 @@ class Cmt2300a { |
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mSpi.writeReg(i, cmtConfig[i]); |
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mSpi.writeReg(i, cmtConfig[i]); |
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} |
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} |
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//uint8_t tmp = (~0x07) & mSpi.readReg(CMT2300A_CUS_CMT10);
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//mSpi.writeReg(CMT2300A_CUS_CMT10, (tmp | 0x02));
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mSpi.writeReg(CMT2300A_CUS_IO_SEL, 0x20); // -> GPIO3_SEL[1:0] = 0x02
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mSpi.writeReg(CMT2300A_CUS_IO_SEL, 0x20); // -> GPIO3_SEL[1:0] = 0x02
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// interrupt 1 control selection to TX DONE
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// interrupt 1 control selection to TX DONE
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@ -377,7 +409,13 @@ class Cmt2300a { |
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} |
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} |
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inline void switchChannel(uint8_t ch) { |
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inline void switchChannel(uint8_t ch) { |
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mSpi.writeReg(CMT2300A_CUS_FREQ_CHNL, ch); |
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mRqstCh = ch; |
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/*DPRINTLN(DBG_INFO, "switchChannel: 0x" + String(ch, HEX));
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if(mInRxMode) |
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mInRxMode = false; |
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cmtSwitchStatus(CMT2300A_GO_STBY, CMT2300A_STA_SLEEP); |
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mSpi.writeReg(CMT2300A_CUS_FREQ_CHNL, ch);*/ |
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} |
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} |
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private: |
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private: |
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@ -386,6 +424,8 @@ class Cmt2300a { |
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mInRxMode = false; |
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mInRxMode = false; |
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mCusIntFlag = 0x00; |
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mCusIntFlag = 0x00; |
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mCnt = 0; |
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mCnt = 0; |
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mRqstCh = 0xff; |
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mCurCh = 0x20; |
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} |
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} |
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// CMT state machine, wait for next state, true on success
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// CMT state machine, wait for next state, true on success
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@ -420,6 +460,7 @@ class Cmt2300a { |
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bool mTxPending; |
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bool mTxPending; |
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bool mInRxMode; |
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bool mInRxMode; |
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uint8_t mCusIntFlag; |
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uint8_t mCusIntFlag; |
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uint8_t mRqstCh, mCurCh; |
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}; |
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}; |
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#endif /*__CMT2300A_H__*/ |
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#endif /*__CMT2300A_H__*/ |
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